LL SBS Constants

HDPL Value

group LL_SBS_HDPL_Value

Defines

LL_SBS_HDPL_VALUE_1 0x00000051U

Hide protection level 1

LL_SBS_HDPL_VALUE_2 0x0000008AU

Hide protection level 2

LL_SBS_HDPL_VALUE_3 0x0000006FU

Hide protection level 3

SBS floating point unit interrupts

group SBS_LL_EC_FLOATING_POINT_UNIT_INTERRUPTs

Defines

LL_SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0

Invalid operation interrupt

LL_SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1

Divide-by-zero interrupt

LL_SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2

underflow interrupt

LL_SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3

Overflow interrupt

LL_SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4

Input abnormal interrupt

LL_SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5

Inexact interrupt

LL_SBS_IT_FPU_ALL

(SBS_FPUIMR_FPU_IE_0 | SBS_FPUIMR_FPU_IE_1 | \

SBS_FPUIMR_FPU_IE_2 | SBS_FPUIMR_FPU_IE_3 | \

SBS_FPUIMR_FPU_IE_4 | SBS_FPUIMR_FPU_IE_5)


All floating point unit interrupts

SBS Erase status Flags

group LL_SBS_Erase_Status_Flags

Defines

LL_SBS_FLAG_IPMEE SBS_MESR_IPMEE

ICACHE erase status flag

LL_SBS_FLAG_MCLR SBS_MESR_MCLR

SRAM2, ICACHE, erase status flag

SBS compensation cell Code source

group SBS_LL_EC_CCELL_CODE

Defines

LL_SBS_CCELL_VDDIO SBS_CCCSR_EN1

Compensation cell selection for VDDIO

LL_SBS_CCELL_CODE_DEFAULT 0U

I/Os code from the cell (available in the SBS_CCVALR)

LL_SBS_CCELL_CODE_CUSTOM 1U

I/Os code from the SBS compensation cell software code register (SBS_CCSWCR)

SBS Vdd compensation cell Code selection

group SBS_LL_EC_CS1

Defines

LL_SBS_CCELL_VDDIO_DEFAULT_CODE 0U

VDD I/Os code from the cell (available in the SBS_CCVALR)

LL_SBS_CCELL_VDDIO_CUSTOM_CODE SBS_CCCSR_CS1

VDD I/Os code from the SBS compensation cell code register (SBS_CCSWCR)

SBS TIM break inputs

group LL_SBS_EC_TIM_BREAK_INPUTS

Defines

LL_SBS_FLASH_ECC_DOUBLE_ERROR SBS_CFGR2_ECCL

Enables and locks the Flash ECC double error signal with Break Input of TIM1/8/15/16/17

LL_SBS_PVD SBS_CFGR2_PVDL

Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input

LL_SBS_SRAM_ECC_DOUBLE_ERROR SBS_CFGR2_SEL

Enables and locks the SRAM ECC double error signal with Break Input of TIM1/8/15/16/17

LL_SBS_LOCKUP_OUT SBS_CFGR2_CLL

Enables and locks the LOCKUP (Hardfault) output of Cortex-M33 with Break Input of TIM1/8/15/16/17

LL_SBS_TIM_BREAK_INPUTS_ALL

(SBS_CFGR2_ECCL | SBS_CFGR2_PVDL | \

SBS_CFGR2_SEL | SBS_CFGR2_CLL)


Enables and locks the all with Break Input

SBS Lock Core Register

group LL_SBS_Lock_Core_Register

Defines

LL_SBS_CPU_LOCK_VTOR SBS_CLCKR_LOCKVTOR

VTOR register lock

LL_SBS_CPU_LOCK_MPU SBS_CLCKR_LOCKMPU

MPU register lock

LL_SBS_CPU_LOCK_ALL (SBS_CLCKR_LOCKMPU | SBS_CLCKR_LOCKVTOR)

All secure registers lock

SBS Next HDP Level Selection

Note

This section is not available for STM32C562xx.

SBS peripheral ETH

Note

This section is not available for STM32C562xx.

SBS Ethernet external PHY interrupt polarity configuration

Note

This section is not available for STM32C562xx.

SBS Ethernet PHY interface selection

Note

This section is not available for STM32C562xx.

SBS Ethernet TXLPI status

Note

This section is not available for STM32C562xx.

SBS Ethernet TXLPI mode status

Note

This section is not available for STM32C562xx.

CHANNEL PIN REMAP

Note

This section is not available for STM32C562xx.